Research at the division of Integrated Circuits and Systems

 

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Brief overview and examples of research work

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Brief overview and examples of research work Division of Integrated Circuits and Systems Department of Electrical Engineering

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Division of Integrated Circuits and Systems – Brief background  A constellation of two former well-established research groups, ‘Electronic Devices’ and ‘Electronics Systems’, merged in 2014.  About 30 years research experience in integrated circuits and systems design.  Internationally recognized as one of the forerunners in high-speed, low power CMOS circuits and signal processing techniques (in most course books).  Several techniques and concepts utilized in commercial products such as advanced microprocessors, wireless sensors, internet routers, CMOS cameras, data acquisition systems, and more.  Strong tradition of collaboration with industry and academia worldwide.  Produced about 8 full Professors, and more than 60 PhDs who are currently with European and U.S. companies, such as Ericsson, SAAB, Infineon, Intel, Broadcom, NXP, etc.  State-of-the-art laboratories and IC design environment.  Provide broad education including about 20 courses at basic and advance levels within digital, analog, and radio frequency integrated circuits and systems.

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Research – Efficient analog, digital, and radio frequency integrated circuits and systems Mixed Analog/Digital • Data converters (ADCs and DACs) for high data-rate communications, low-power sensors, and medical implant devices. • High-precision analog readout and data acquisition for image sensors and other massive parallel sensors . • Integrated power management systems and power converters for energy harvesting. • On-chip clock generators, frequency synthesizers, and timing/synchronization. • High-speed on-chip/off-chip communication links and I/O interface. Digital • High-performance and low-power integrated digital processing circuits and systems. • On-chip networks and on-chip memories. Radio Frequency (RF) IC • Energy-efficient RF CMOS power amplifiers and radio transmitter front-ends. • Flexible RF sampling receiver front-ends for software defined radio. • Low-power wireless transceivers for wireless sensors.. Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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Examples of IC design projects and results * The material will be updated every year to include new examples of the ongoing projects and our latest published research work. Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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Examples of IC design projects and results Efficient Data Converters (ADCs and DACs) Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 130 nm CMOS for medical implant devices, particularly for pacemakers *1' 9''+ & & & & 9'$&3 &287 9''+ 63 6ZLWFKHV &RPSDUDWRU '$& 6$5 /HYHO6KLIWHUV 3RZHU 0DQDJHPHQW 9,13 $'& 9,11 9'$&1 61 & & & & 6DPSOH &RQWURO 6LJQDOV 6HQVLQJ )LOWHULQJ $PSOLI\LQJ 9''+ *1' 9''+ 9''/ 9''/ &/. 567 3URJUDPPDEOH/RJLF 7KHUDS\$OJRULWKPV 3DFH 'ULYHU 3XOVH *HQHUDWRU ,PDJHFRXUWHV\$PHULFDQ+HDUW $VVRFLDWLRQ 9ROWDJH/HYHO6KLIWHUV 6XFFHVVLYH$SSUR[LPDWLRQ5HJLVWHU 'a' (12%>ELW@  '1/>/6%@                    1RUPDOL]HG) ) ,1 6 $XWKRU —P@  &ORFN /DWFK 6DXHUEUH\ %HFKHQ >@ >@           =RX >@      7KLV :RUN      6DPSOH5DWH>N6V@ 3RZHU>Q:@ (12%>ELW@ )R0>I-&RQY@ ,1/>/6%@         2XWSXW&RGH  36'>G%@       )UHTXHQF\>IIV@     Lowest reported power consumption (53 nW) LQfor ADCs for such applications! D. Zhang, A. Bhide, and A. Alvandpour, ”A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-ʅŵDK^ĨŽƌ DĞĚŝĐĂů/ŵƉůĂŶƚĞǀŝĐĞƐ͕͟ŝŶ/:ŽƵƌŶĂůŽĨ^ŽůŝĚ-State Circuits, vol.47, no.7, pp.1585-ϭϱϵϯ͕:ƵůLJϮϬϭϮ͘ Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s in 65nm CMOS, for medical implant devices and ultra-low-power sensors. VREF VIN C 16C C C C 16C C 16C VIP VREF Reset C 16C VDD 0 DNL [LSB] 0.5 [-0.55, +0.48] 0 -0.5 0 200 400 600 800 1000 COUT PSD [ dB ] -50 -100 0 SNDR = 56.6dB; ENOB = 9.1bit THD = -68.9dB; SFDR = 74.5dB Successive Approximation Control Logic VDD CLK RST 0.1 0.2 0.3 Frequency [ f / f ] s 0.4 0.5 INL [LSB] 0.5 [-0.61, +0.52] 0 -0.5 0 200 600 400 code 800 1000 DOUT Single supply low-voltage (700mV) and multi-Vt design Lowest reported power consumption of 3 nW, pushed the power limits in 2012, as compared to previously lowest reported power, also from us (in previous slide) D. Zhang, A. Alvandpour, ”A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s”, in proceedings of the European Solid-State Circuit Conference (ESSCIRC), pp.369-372, Bordeaux, France, September 2012 Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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Low-Power ADC DT '6 modulators using SC passive (OTA-less) filters in 65nm CMOS 3DVVLYHVWDJH &ORFN*HQHUDWRU 95()3 95()1 /S ɎG LQS ɎG /Q &6 &, Ɏ 95()3 95()1 /S /Q &6 &, Ɏ ɎG Ɏ 3DVVLYHJDLQ ERRVW &DSDFLWRUV  /S 3UHDPS 4XDQWL]HU  Ɏ Ɏ FPL  27$ ɎG  Ɏ FPL Ɏ  27$  3DVVLYHVWDJH 4XDQWL]HU LQQ ɎG ɎG /S &6 /Q Ɏ   ɎG ɎG &6 /Q Ɏ   &,   /Q &DSDFLWRUV &ORFN*HQHUDWRU &DSDFLWRUV QGLQWHJUDWRU &, /S VWLQWHJUDWRU 4XDQWL]HU 95()1 95()3 95()1 95()3 ǻȈ0$3 &RUH Active filters in both stages ('6AA) 3DVVLYH,QWHJUDWRU 95()3 95()1 /S ɎG LQS ɎG /Q &6 Ɏ Ɏ &6 /Q Ɏ &, Ɏ   FPL 27$   &, 95()3 95()1 &ORFN*HQ ǻȈ033 &RUH ǻȈ0$$ &RUH QGLQWHJUDWRU VWLQWHJUDWRU Ɏ Ɏ FPL LQQ ɎG ɎG /S ɎG ɎG /S &6 /Q Ɏ & SUHDPS   /S ɎG ɎG /Q & &6 Ɏ     /S Ɏ &DSDFLWRUV &DSDFLWRUV     /Q  7HFKQRORJ\ 6XSSO\9ROWDJH &ORFN)UHTXHQF\ 6LJQDO%: 3HDN615 3HDN61'5 '\QDPLF5DQJH 3RZHU $FWLYH$UHDPP )20:S-VWHS '60$$ '60$3 '6033 99 N+] 95()1 95()3 95()1 95()3 30QP&026 Passive filter in 95()3 95()1 2nd Ɏ stage '6$3  &6 Ɏ Ɏ Ɏ &6 Ɏ Ɏ & Ɏ   SUHDPS 9 N+] G% G% G% ȝ:   /S /Q Ɏ Ɏ &6 Ɏ Ɏ 95()3 95()1 /S Ɏ LQS Ɏ Ɏ Ɏ /S /Q &6 Ɏ Ɏ &6 /Q & Ɏ FPL Ɏ & FPL   /S LQQ   95()1 95()3   /Q FPL /S /Q Ɏ Ɏ &6 Ɏ Ɏ Ɏ &6 Ɏ Ɏ Ɏ &6 Ɏ Ɏ & 95()195()3 Passive filter in both stages (OTA-less modulator, '6$3 +] G% G%G% G%G% G% G% G%G% ȝ: ȝ:ȝ:     A. Fazli, F. Qazi, and A. Alvandpour, “Low-WŽǁĞƌdȴɇDŽĚƵůĂƚŽƌƐhƐŝŶŐ^WĂƐƐŝǀĞ&ŝůƚĞƌƐŝŶϲϱŶŵ CMOS,” In IEEE Transaction on Circuits and Systems I, pp. 358-370, Vol. 61, No. 2, Feb 2014 Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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A compact 16-bit ADC for infrared readout IC • Utilized in a column-parallel readout structure • Compact architecture and shared circuitry allows individual channels fit in a 25-μm pitch • Chopper stabilization reduces offset and 1/f noise Process Sample Rate SNDR THD Dynamic Range - ADC Channel power - Common Circuitry ADC Channel 0.35 μm CMOS 23.32 kHz (60 fps) 86 dB -96 dB 90 dB 570 μW 24 mW (292 channels) 0.018 mm2 (25x720 μm) D. Svärd, C. Jansson, and A. Alvandpour, “A readout IC for an uncooled microbolometer infrared FPA with on-chip self-heating compensation in 0.35 μm CMOS”, in Analog Integrated Circuits and Signal Processing, vol. 77, pp. 29 - 44, October 2013 Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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A Vernier time-to-digital converter with delay latch chain architecture High-level architecture Detailed implementation N.U. Andersson and M. Vesterbacka, “A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture,” IEEE Trans. Circuits Syst. Part II: Express Briefs, vol. 61, no. 10, pp. 773-777, Oct. 2014. Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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Synthesizable all-digital ADCs Example: A time-mode ADC in 65nm CMOS using standard cells ‡ Signal represented and processed in time instead of voltage/current. ‡ Ring VCO based noise-shaping, all-digital ‡ Exclusive use of vendor supplied standard cells ‡ Spurious-error mitigation using Gray-counter based phase accumulation ‡ Lowest reported power consumption and best FoM in class s͘hŶŶŝŬƌŝƐŚŶĂŶĂŶĚD͘sĞƐƚĞƌďĂĐŬĂ͕ΗdŝŵĞ-mode analog-to-ĚŝŐŝƚĂůĐŽŶǀĞƌƐŝŽŶƵƐŝŶŐƐƚĂŶĚĂƌĚĐĞůůƐ͕ΗŝŶ /dƌĂŶƐĂĐƚŝŽŶƐŽŶŝƌĐƵŝƚƐĂŶĚ^LJƐƚĞŵƐ/͕sŽůƵŵĞϲϭ͕/ƐƐƵĞϭϮ͕ƉƉ͘ϯϯϰϴ- ϯϯϱϳ͕ĞĐĞŵďĞƌϮϬϭϰ Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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Energy-efficient high-speed Flash ADCs Example: A low-power 4-bit, 1.5 to 2.5 GHz Flash ADC in 90nm CMOS • Redundancy-based flash ADC, 63 small-sized comparators for 4-6 bits of resolution. • Calibration by disabling bad comparators • The ADC utilizes native mismatches (process variations) and redundancy to generate the references voltages without using reference ladder. Author Year Park. 2007 Park, 2005 Sheikhaei, 2007 Deguchi, 2007 Lin, 2007 Van der Plas, 2007 Proposed Flash ADC Proposed reference-free Flash ADC ENOB 3.9 5.5 3.2 4.9 4.2 3.7 3.9 3.7 Sampling Freq. 4 GS/s 2 GS/s 3.0 GS/s 3.5 GS/s 4.2 GS/s 1.25 GS/s 2.5 GS/s 1.5 GS/s CMOS Process 0.18µm 0.18µm 0.18µm 90nm 0.13µm 90 nm 90nm 90nm Power 608 mW 145 mW 43 mW 98 mW 180 mW 2.5 mW 30 mW 23 mW FoM pJ/ConvStep 20.4 6.41 1.51 0.95 2.80 0.15 3.15 1.47 T. Sundström and A. Alvandpour, “Utilizing Process Variations for Reference Generation in a Flash ADC”, in IEEE Trans. Circuits and Systems II, Vol 56, Issue 5, pp. 364 - 368, May 2009. T. Sundström and A. Alvandpour, ”A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS,“ in Analog Integrated Circuits and Signal Processing, Vol.64, pp. 215-222, Aug 2010. Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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High-speed pipeline ADCs for wideband communications Example: A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS • Clocking scheme removes the comparator latency from the critical path. • Fast open-loop amplifiers • Digital calibration, corrects for stage gain-error and input-stage non-linearity. Author Year Shen JSSC-07 Varzaghani JSSC-09 Nazemi VLSI-08 This Work Architecture Pipeline Interleaved Pipeline Interleaved Pipeline Pipeline CMOS Process 0.18µm 0.13µm 90nm 65nm Sample Rate (GS/s) 0.8 4.8 10.3 2.0 2.2 2.4 ENOBmin DC-Nyquist 4.9 4.7 5.1 5.3 4.9 4.7 Power (mW) 105 300 1600 294 310 318 FoM (pJ/convstep) 3.3 2.3 2.8 2.7 3.4 3.2 Fastest reported CMOS pipeline ADC in 2011 T. Sundström, C. Svensson, A. Alvandpour, “A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS,” in IEEE Journal of Solid State Circuits, vol. 46, pp. 1575-1584, July 2011 Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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An 8-GS/s 200-MHz bandwidth 68-mW ∆Σ DAC in 65-nm CMOS for wideband radio transmitters Two-channel interleaved 8GS/s at 200 MHz BW 57dB IM3, 48dB SFDR, 26dB SNDR. 68mW power consumption. 1.5X higher sampling rate and 2X higher bandwidth, compared to previously reported ∆Σ DACs. A. Bhide, O. E. Najari, B. Mesgarzadeh, and A. Alvandpour, “An 8-GS/s 200-MHz Bandwidth 68-mW ∆Σ DAC in 65-nm CMOS”, in IEEE. Transactions on Circuits and Systems II, vol. 60, pp. 387-391, July 2013. Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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Examples of IC design projects and results Wireless sensors Division of Integrated Circuits and Systems, Dept. of Electrical Engineering, Linköping University

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